Among high-precision AD converters, a ΔΣ AD converter is currently preferred as an AD converter for industrial applications. In a case of AD conversion of sensor signals, for example, the AD converter may be required to perform conversion of a plurality of inputs from the sensor. In an example application, a pressure sensor measures a differential pressure, a static pressure, and a temperature to adjust the properties of the sensor by performing an internal arithmetic operation. At this time, it is desirably required that the respective sensor outputs be obtained simultaneously. Accordingly, a plurality of ΔΣ AD converters each constituted by a ΔΣ modulator 100 and a digital filter 101 are provided in the prior art, as illustrated in FIG. 8, to process the plurality of sensor outputs. The configuration illustrated in FIG. 8 is typically formed on a single silicon chip.
The digital filter 101 (LPF: Low Pass Filter) used in the ΔΣ AD converter is also known by the name of decimation filter. As the decimation filter, a SINC filter having a simple internal configuration is preferably used. The SINC filter can be expressed by the transfer function (1−z−N)/(1−z−1). By increasing the order of the ΔΣ modulator used in the ΔΣ AD converter, an increased effect of noise shaping can be achieved. It is well known that the order of the decimation filter (SINC filter) in the subsequent stage needs to be made higher than the order of the ΔΣ modulator.
Now, an AD converter using a second-order ΔΣ modulator, for example, is considered. As the SINC filter, a third-order filter is necessary, as illustrated in FIG. 9. The SINC filter is expressed by the transfer function {(1−z−N)/(1−z−1)}^3. Here, a technique is well known in which an integration calculation unit that represents the denominator of the transfer function is separated from a difference calculation unit that represents the numerator of the transfer function, and the difference calculation unit is placed after down-sampling at a frequency 1/N. In the example illustrated in FIG. 9, the SINC filter is configured such that integration calculation units 200 in three stages that are cascade-connected and difference calculation units 201 in three stages that are cascade-connected are connected via a frequency conversion unit 202. The frequency conversion unit 202 is formed of a flip-flop 203 illustrated in FIG. 10. The integration calculation units 200 operate at a sampling frequency fs, and the difference calculation units 201 and the frequency conversion unit 202 operate at a sampling frequency fD=fs/N.
In the configuration illustrated in FIG. 9, both the integration calculation units and the difference calculation units are constituted by digital circuits, and therefore, their signal lines have a bit width of a plurality of bits. The bit width needs to be selected so as not to cause internal saturation. The bit width depends on the frequency ratio N for down-sampling and needs to be equal to K×log2(N)+1[bit] (see literature “J. C. Candy and G. C. Temes, “Oversampling Delta-Sigma Data Converters”, IEEE Press, pp. 1-29, 1991″). Here, K is the number of stages of the filter. If the SINC filter is a third-order filter, as illustrated in FIG. 9, K=3 is satisfied. In a case where 16-bit precision is required when N=256, for example, 25 bits are necessary. Therefore, a register that corresponds to the bit width is necessary.
Accordingly, a register that corresponds to the bit width of data is necessary for a digital filter. The circuit scale of an addition circuit and a subtraction circuit used to add and subtract data within the register becomes larger as the bit width increases. In industrial applications, high bit resolution and high precision are much desired, and therefore, the output from a digital filter often ranges from 16 bits to 24 bits. Accordingly, the circuit scale increases. Further, if a plurality of AD converters are provided for a plurality of inputs, as illustrated in FIG. 8, the ΔΣ modulator 100 and the digital filter 101 need to be provided for each input, resulting in a significant increase in the circuit scale.
Regarding a multi-input ΔΣ modulator that processes a plurality of inputs, a configuration with which the circuit scale and cost are reduced is proposed in Japanese Patent No. 4171222; however, a method for reducing the circuit scale and cost of a multi-input digital filter is not known.